1. Technical Field of the Invention
The present invention generally relates to semiconductor processing techniques. More particularly, the present invention relates to selective modification of the interconnects of an integrated circuit to achieve improved mechanical and electrical properties.
2. Description of Related Art
The semiconductor technology central to the modern integrated circuit (“IC”) has been developing for over a century. In the late nineteenth century, the special properties of the semiconductor selenium were first observed and recognized. The field of semiconductor physics advanced rapidly and the first transistor was proposed in the 1930s. However, not until the late 1940s was a functional point contact transistor constructed. The IC, which employs a plurality of circuit elements in a monolithic semiconductor substrate rather than using discrete components, was first developed in the late 1950s by Jack Kilby at Texas Instruments, Inc. and by Robert Noyce at Fairchild Semiconductor Corporation.
Since the late 1950s, IC technology has evolved rapidly and has revolutionized virtually every industry and capacity in which ICs are used. Today's ICs frequently employ hundreds of thousands or even millions of transistors and highly complex, multi-layered architectures. The proliferation of electronics in general, and ICs in particular, has resulted in large part from the ability to increase circuit functionality while simultaneously reducing device cost and size. An important catalyst for these improvements has been advances in semiconductor processing technologies. Although a wide array of semiconductor companies and products exist, for the most part, semiconductor processing is completed through a series of common steps. Semiconductor processing begins with a wafer or substrate, upon which various processing techniques are used to construct circuit elements such as transistors, resistors and capacitors. The formation of circuit elements comprises a process called doping—i.e., deliberately introducing impurities into certain regions of the monolithic crystalline substrate. After the circuit elements are formed, a series of conductive and insulating layers are used to form connections, called interconnects, between the appropriate circuit elements.
As increasingly complex ICs utilize an increasing number of circuit elements, more electrical interconnects between circuit elements and a greater number of conductor-insulator layers are required. A chief objective of semiconductor processing is the minimization of interconnect electrical resistance. Increased resistance is undesirable because as the interconnect resistance between two electrical devices increases, so too does the amount of time it takes a signal to propagate between the devices. This, in turn, decreases the overall speed at which the IC functions. Additionally, increased resistance also increases the amount of overall power consumed by the IC.
Another important consideration is the mechanical stability of the interconnects, which is negatively impacted by a phenomenon known as electromigration, the migration of atoms in the interconnect induced by applying an electric potential across the interconnect. The principle of electromigration is depicted graphically in FIGS. 1A, 1B and 2. FIG. 1A shows an electron flow 14 in a conductor 10 due to a potential difference supplied by a battery 12. The momentum of the electrons in the electron flow 14 causes atoms in the conductor 10 to migrate in the same direction as the electron flow 14. Grain boundaries occur at the intersection between two crystalline grains. The intersection of three or more crystalline grains may be susceptible to electromigration. Consequently, grain boundary 16 and intersection point 18 are likely places for electromigration damage, but usually at higher activation energy than surface diffusion in the case of Cu metallization.
FIG. 1B shows electron flow 14 through grain boundary intersection points 18A and 18B. In intersection point 18A, electron flow 14 from two grains is merging into a single grain, resulting in the formation of void 20. In intersection point 18B, in contrast, electron flow 14 from a single grain is diverging into two different grains, resulting in the formation of hillock 21.
Conductors are often processed using aluminum with a small concentration (i.e., less than about 2% by weight), of Copper (“Cu”). More recently, pure Cu has been the metal of choice for producing metal interconnect on ICs. To contain the Cu and keep it from entering and moving within the glass dielectric layers and the active areas of the substrate, barrier layers surround the Cu. These barriers are carefully chosen so as to not cause adhesion problems between the metallization and the encapsulating/insulating dielectric layers. With the advancement of technology, new materials are sought to reduce parasitic capacitance and resistance for greater circuit performance and lower power consumption. These new materials possess lower dielectric constants but also lower thermal conductance. This reduces the efficiency with which heat is transferred to the substrate. Also, these material are more brittle and mechanically less robust than the more traditional silicone dioxide. Lower mechanical strength means less resistance to cracking and possibly a greater tendency toward electromigration, due to tensile forces on the metallization or lower strength in general. The surface between the Cu lead and the barrier is observed to be a path for metal movement of relatively low activation energy. Voids can nucleate and/or grow at this surface, and the other interfacial surfaces. Metal will electromigrate, that is, drift or diffuse in the direction of electron flow under electrical bias. Voids, depletion of metal in an area, can form near the electron source. These voids are usually paired downstream with hillocks, an accumulation of metal. Hillocks can cause the formation of metal filaments into the dielectric, that is, unwanted paths of current leakage, and even cracking of the barrier and/or dielectric.
The impact on circuit performance of void 20 and hillock 21 in FIG. 1 is depicted graphically in FIG. 2. FIG. 2 shows interconnect 23 and parallel interconnect 24, which is desirably electrically isolated from interconnect 23. Proper circuit performance requires not only high electrical conductance along interconnect 23 and interconnect 24 but a high electrical resistance between them. Void 20 and hillock 21 can impact both the electrical conductance along a single interconnect and the electrical resistance between two different interconnects. For example, void 20 in interconnect 23 can significantly decrease the electrical conductance along interconnect 23. Similarly, hillock 21 can create a short between interconnect 23 and interconnect 24, thereby destroying the electrical isolation between the two interconnects.
Voids can also arise from stress. Interconnects frequently abut adjacent layers formed at different temperatures. For example, a copper interconnect deposited at room temperature may adjoin a carbide layer formed at around 400° C., thereby causing an inherent stress. Tensile stresses in the interconnect tend to pull the interconnect material apart (causing voids) as the interconnect changes temperatures, further exacerbating migration problems. This effect is more prevalent at the interface between adjacent layers. Furthermore, this stress voiding at the interfacial surfaces is even more problematic at elevated temperatures and/or under heavy current flow.
Until recently, aluminum was the interconnect conductor of choice in IC processing. The popularity of aluminum stemmed from a variety of factors. First, techniques for depositing thin aluminum films are well established. Second, because aluminum can be etched effectively in chlorine plasmas, the formation of patterned aluminum films is relatively straightforward. Unfortunately, though, aluminum interconnects have several drawbacks. First, from an electrical perspective, aluminum is relatively poor conductor relative to other metals. Consequently, aluminum negatively impacts circuit speed and power usage. Second, from a mechanical perspective, aluminum is particularly susceptible to structural problems resulting from electromigration and stress. For years, the semiconductor industry has been moving away from aluminum metallization. Initial efforts included adding trace amounts of copper to the aluminum, because the copper had a lower resistivity and was less susceptible to electromigration. With each successive generation of ICs more copper was added.
Currently, the semiconductor industry is transitioning to pure—or relatively pure—copper as the electrical conductor of choice for establishing interconnections between circuit elements. Copper has a significantly higher conductivity than aluminum and is inherently more resistant to electromigration. Procedures such as chemical mechanical polishing (“CMP”) are facilitating the shift to copper metallization. In general, CMP involves planarizing surface layers that have been deposited on a semiconductor wafer.
While the shift to copper interconnects has alleviated some of the problems associated with aluminum metallization, it has not eliminated them. Although less susceptible, copper also suffers from electrically-induced and stress-induced migration problems. Electromigration problems with copper were recently discussed in “Binary Cu-Alloy Layers for Cu-Interconnections Reliability Improvement” by Connie P. Wang et al. (hereinafter “Wang”). According to Wang, current techniques for dealing with electromigration problems in copper interconnects include the use of copper alloys that exhibit improved structural stability over pure copper. In general, Wang's approach involves selecting copper alloys, rather than copper, to fill the interconnect trench. Because copper alloys frequently exhibit increased electrical resistance to current flow, Wang focused on those copper alloys possessing suitably low electrical resistance. Using this criteria, Wang limited the copper alloy materials to CuSn, CuIn, and CuZr, for which the additional sheet resistance ranges from 1.1-18 μΩ-cm.
The use of copper alloys rather than copper creates several problems. First, copper interconnects comprised entirely of these copper alloys (e.g., CuSn, CuIn, CuZr, etc.) exhibit larger sheet resistances than pure copper interconnects. This added electrical is especially problematic for long thin metal interconnects.
Second, the copper alloys disclosed by Wang are not conventionally used in other manufacturing steps. Consequently, these materials raise process integration issues and likely would lead to significantly increased manufacturing costs.
A need still exists for improved copper metallization that possesses improved mechanical stability without increased electrical resistance.